1. Field of the Invention
The present invention relates to the field of emulation. More specifically, the present invention relates to emulation components, such as emulation integrated circuits (IC) and logic boards, emulation systems formed with such components, as well as emulation resource allocation/configuration and debugging/testing methodologies practiced therein.
2. Background Information
The first generation of prior art emulation systems were typically formed using general purpose FPGAs without integrated debugging facilities. To emulate a circuit design on one of such emulation systems, the circuit design would be “realized” by compiling a formal description of the circuit design, partitioning the circuit design into subsets, mapping the various subsets to the logic elements (LEs) of the FPGAs of various logic boards of the emulation system, and then configuring and interconnecting the LEs. The partitioning and mapping operations would be typically performed on workstations that are part of or complementary to the emulation systems, while the configuration information would be correspondingly downloaded onto the logic boards hosting the FPGAs, and then onto the FPGAs.
During emulation, test stimuli are either generated on the workstation or on a service board of the emulation system under the control of the workstation, and then transfer to the various logic boards for input into the emulation ICs for application to the various netlists of the IC design being emulated. State data of various circuit elements as well as signal states of interest of the IC design being emulated, would be correspondingly read out of the applicable FPGAs, and then transfer off the logic boards, for analysis on the workstation.
With advances in integrated circuit and emulation technology, some late model emulation systems would employ “FPGAs” specifically designed for emulation purpose. These special “FPGAs” or emulation ICs typically would include substantial amount of on-chip reconfigurable logic elements, inteconnects, memory as well as debugging resources. As the advances continue, more and more of these resources are packed into each emulation IC. As a result, more and more control signals have to be transferred onto each logic board (for transfer into the emulation ICS) to configure the emulation ICs of the logic board. Likewise, more and more state elements and/or signals of interest of the emulation ICs have to be transferred out of the emulation ICs and logic boards to facilitate analysis, leading to the formation of various bottlenecks, in particular, at the logic boards, preventing efficient operation of the emulation systems.
Thus, an improved approach to forming and operating emulation systems is desired.